View AD7934BRUZ-6_4194026.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-channel, 625 ksps, 12-bit parallel adc with a sequencer ad7934-6 rev. a in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th i r d p a r t i e s th a t m a y r e su l t fr o m it s u s e . s p e c if i c a t io n s s u bj e c t t o ch an g e w i th o u t n o ti c e . n o l i c e n s e is g r an t e d b y i m p l ica t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g de v i c e s . t r adem ar ks and r e g i st er ed tr adem ar ks ar e the pr op er t y o f th e i r r e s p ec t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures t h ro ughput r a te: 62 5 ksps specified f o r v dd of 2.7 v t o 5. 25 v p o w e r c o nsumption 3.6 mw m a x a t 625 ksps with 3 v sup p lies 7.5 mw m a x a t 625 ksps with 5 v sup p lies 4 analog input channels with a sequenc e r s o f t war e c o nfigur able ana l og inputs 4- channel singl e - ended inputs 2- channel f u ll y dif f er ential in puts 2- channel pse u do dif f er ential inputs a c cur a t e on- c hip 2.5 v re f e ren c e 0.2% m a x @ 25c, 25 p p m/c ma x 70 db sinad a t 50 k hz inpu t frequenc y n o pipeline dela y s high speed par a llel int e r f ac e w o r d /byt e m o des f u ll sh ut down mode: 2 a m a x 28-lea d t ssop pack age func ti on a l bl ock di a g r a m 04752-001 v in 3 t/h parallel interface/control register sequencer 12-bit sar adc and control i/p mux 2.5v vref db0 db11 v drive v dd ad7934-6 v in 0 agnd v refin/ v refout clkin busy convst cs dgnd rd wr w/b figure. 1 gener a l description the ad7934 -6 is a 12-b i t, hig h s p ee d , lo w p o wer , s u cces si v e a p p r o x ima t io n (sar) a n alog-to-dig i tal co n v er t e r (ad c ). th e p a r t o p era t es f r o m a sing le 2.7 v t o 5.25 v p o w e r s u p p l y a nd f e a t ur es thr o ug h p u t ra t e s u p t o 625 ks ps. th e p a r t co n t a i n s a lo w n o i s e, wi de b a ndwi d t h , dif f er en t i a l t r ack - and- h o ld a m plif ier t h a t h a n d les in p u t f r e q uen c ies u p t o 50 mh z. th e ad7934-6 f e a t ur es f o u r a n al og in p u t c h a n n e ls wi th a c h a n n e l s e q u e n c e r t h a t a l lo ws a p r ep r o g r a m m e d s e le c t i o n o f cha nnels to b e c o nv e r t e d s e q u e n t i a l l y . t h i s p a r t c a n a c c e pt ei t h e r s i ng l e - en de d , f u l l y dif f er en t i a l , o r ps eudo di f f er en t i a l a n alo g in p u ts. d a t a acq u i s i t io n a n d co n v ersi o n a r e co n t r o l l e d b y st a n da r d co n t r o l in p u ts, w h ich a l lo w fo r e a sy in ter f acin g t o m i cr o p r o cess o r s a n d ds p s . th e in p u t sig n a l is s a m p le d o n t h e fal l in g e d ge o f co n v s t , w h ich is als o t h e p o in t w h er e t h e con v ersion is ini t i a t e d . the ad7934 -6 has a n acc u ra t e o n -c hi p 2.5 v r e f e r e n c e tha t c a n b e u s e d a s t h e re f e re nc e s o u r c e f o r t h e an a l o g - t o - d i g i t a l co n v ersio n . al ter n a t i v e l y , t h is p i n c a n b e o v er dr i v en t o p r o v i d e an e x te r n a l re f e re nc e. th e ad7934-6 u s es ad va n c ed de s i g n t e c h niq u es t o ac hiev e v e r y l o w p o w e r d i s s i p at i o n at h i g h t h ro u g hp u t r a t e s . t h e p a r t a l s o f e a t u r e s f l ex ibl e p o we r m a n a ge m e n t opt i ons . a n on - c h i p con t ro l r e g i s t er allo ws t h e us e r t o s e t u p dif f e r en t o p e r a t in g co n d i t io n s , in cl udin g a n a l og in p u t ra n g e a n d co n f igura t io n, o u t p u t co din g , p o w e r ma na gem e n t , a n d cha n n e l s e q u en cin g . produc t highlight s 1. h i gh th r o ugh p u t w i th lo w po w e r co n s um p t i o n . 2. f o u r a n al og in p u ts wi th a c h a n n e l s e q u en ce r . 3. a c c u ra t e o n -c hi p 2. 5 v r e f e r e n c e . 4. sin g le-en d e d , pseudo di f f er en t i a l , o r fu lly dif f er en tia l a n a l o g i n p u t s th a t a r e so ft w a r e se l e cta b l e . 5. n o p i p e lin e de la y . 6. a c c u r a te c o n t r o l of t h e s a m p l i ng inst an t v i a a co n v s t in p u t a n d o n ce o f f co n v er sio n c o n t r o l . table 1. r e lated d e vices similar de vic e number of bits number of channels speed a d 7 9 3 8 / 3 9 1 2 / 1 0 8 1.5 m s p s a d 7 9 3 3 / 3 4 1 0 / 1 2 4 1.5 m s p s a d 7 9 3 8 - 6 1 2 8 625 k s p s
ad7934-6 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 ter mi nolo g y ...................................................................................... 9 typical performance characteristics ........................................... 11 control register .............................................................................. 13 sequencer operation ................................................................. 14 note on writing to the control register to program the sequencer ............................................................. 14 circuit information ........................................................................ 15 converter operation .................................................................. 15 adc transfer function ............................................................. 15 typical connection diagram ................................................... 16 analog input structure .............................................................. 16 analog input configurations ................................................... 17 analog input selection .............................................................. 19 reference section ....................................................................... 20 parallel interface ......................................................................... 21 power modes of operation ....................................................... 24 power vs. throughput rate ....................................................... 25 microprocessor interfacing ....................................................... 25 application hints ........................................................................... 27 grounding and layout .............................................................. 27 evaluating the ad7934-6 performance .................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 10/05rev. 0 to rev. a changes to product highlights....................................................... 1 inserted table 1................................................................................. 1 changes to specifications ................................................................ 3 changes to timing specifications .................................................. 5 changes to pin function descriptions.......................................... 7 added writing to the control register to program the sequencer section.................................................... 14 changes to the analog inputs section......................................... 17 changes to the grounding and layout section ......................... 27 1/05revision 0: initial version
ad7934-6 rev. a | page 3 of 28 specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted, f clkin = 10 mhz, f sample = 625 ksps; t a = t min to t max 1 , unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 70 db min differential mode 68 db min single-ended mode signal-to-noise ratio (snr) 2 71 db min differential mode 69 db min single-ended mode total harmonic distortion (thd) 2 ?73 db max ?85 db typ, differential mode ?70 db max ?80 db typ, single-ended mode peak harmonic or spurious noise (sfdr) 2 ?73 db max ?82 db typ intermodulation distortion (imd) 2 fa = 30 khz, fb = 50 khz second-order terms ?86 db typ third-order terms ?90 db typ channel-to-channel isolation ?85 db typ f in = 50 khz, f noise = 300 khz aperture delay 2 5 ns typ aperture jitter 2 72 ps typ full power bandwidth 2 50 mhz typ @ 3 db 10 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max differential mode 1.5 lsb max single-ended mode differential nonlinearity 2 differential mode 0.95 lsb max guaranteed no missed codes to 12 bits single-ended mode ?0.95/+1.5 lsb max guaranteed no missed codes to 12 bits single-ended and pseudo differential in put straight binary output coding offset error 2 6 lsb max offset error match 2 1 lsb max gain error 2 3 lsb max gain error match 2 1 lsb max fully differential input twos complement output coding positive gain error 2 3 lsb max positive gain error match 2 1 lsb max zero-code error 2 6 lsb max zero-code error match 2 1 lsb max negative gain error 2 3 lsb max negative gain error match 2 1 lsb max analog input single-ended input range 0 to v ref v range bit = 0 0 to 2 v ref v range bit = 1 pseudo differential input range: v in+ 0 to v ref v range bit = 0 0 to 2 v ref v range bit = 1 v in? ?0.3 to +0.7 v typ v dd = 3 v ?0.3 to +1.8 v typ v dd = 5 v fully differential input range: v in+ and v in? v cm v ref /2 v v cm = v ref /2 3 , range bit = 0 v in+ and v in? v cm v ref v v cm = v ref 3 , range bit = 1 dc leakage current 4 1 a max input capacitance 45 pf typ when in track 10 pf typ when in hold
ad7934-6 rev. a | page 4 of 28 parameter b version 1 unit test conditions/comments reference input/output v ref input voltage 5 2.5 v 1% for specified performance dc leakage current 4 1 a max v refout output voltage 2.5 v 0.2% max @ 25c v refout temperature coefficient 25 ppm/c max 5 ppm/c typ v ref noise 10 v typ 0.1 hz to 10 hz bandwidth 130 v typ 0.1 hz to 1 mhz bandwidth v ref output impedance 10 ? typ v ref input capacitance 15 pf typ when in track 25 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in 5 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh 2.4 v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 3 a max floating-state output capacitance 4 10 pf max output coding coding bit = 0 straight (natural) binary twos complement coding bit = 1 conversion rate conversion time t 2 + 13 t clk ns track-and-hold acquisition time 125 ns max full-scale step input 80 ns typ sine wave input throughput rate 625 ksps max power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 6 digital i/p s = 0 v or v drive normal mode (static) 0.8 ma typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 1.5 ma max v dd = 4.75 v to 5.25 v 1.2 ma max v dd = 2.7 v to 3.6 v autostandby mode 0.3 ma typ f sample = 100 ksps, v dd = 5 v 160 a typ static, v dd = 3 v full/autoshutdown mode (static) 2 a max sclk on or off power dissipation normal mode (operational) 7.5 mw max v dd = 5 v 3.6 mw max v dd = 3 v autostandby mode (static) 800 w typ v dd = 5 v 480 w typ v dd = 3 v full/autoshutdown mode 10/6 w max v dd = 5 v/3 v 1 temperature range is as follows: b version: C40c to +85c. 2 see the section. terminology 3 v cm is the common-mode voltage. for full common-mode range, see figur and . v e 25 figure 26 in+ and v in? must always remain within gnd/v dd . 4 sample tested during initial release to ensure compliance. 5 this device is operational with an exte rnal reference in the range 0.1 v to v dd . see the r for more information. eference sectio n 6 measured with a midscale dc analog input.
ad7934-6 rev. a | page 5 of 28 timing specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted. f clkin = 10 mhz, f sample = 625 ksps, t a = t min to t max , unless otherwise noted. table 3. parameter 1 limit at t min , t max unit description f clkin 2 700 khz min clkin frequency 10 mhz max t quiet 30 ns min minimum time between end of read and start of next conversion, that is, time from when the data bus goes into three-state until the next falling edge of convst t 1 10 ns min convst pulse width t 2 15 ns min convst falling edge to clkin falling edge setup time t 3 50 ns min clkin falling edge to busy rising edge t 4 0 ns min cs to wr setup time t 5 0 ns min cs to wr hold time t 6 10 ns min wr pulse width t 7 10 ns min data setup time before wr t 8 10 ns min data hold after wr t 9 10 ns min new data valid before falling edge of busy t 10 0 ns min cs to rd setup time t 11 0 ns min cs to rd hold time t 12 30 ns min rd pulse width t 13 3 30 ns max data access time after rd t 14 4 3 ns min bus relinquish time after rd 50 ns max bus relinquish time after rd t 15 0 ns min hben to rd setup time t 16 0 ns min hben to rd hold time t 17 10 ns min minimum time between reads/writes t 18 0 ns min hben to wr setup time t 19 10 ns min hben to wr hold time t 20 40 ns max clkin falling edge to busy falling edge t 21 15.7 ns min clkin low pulse width t 22 7.8 ns min clkin high pulse width 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. all timing specifications given above are with a 25 pf load ca pacitance. see , , , and . figure 34 figure 35 figure 36 figure 37 2 minimum clkin for specified performance. with slower clkin frequencies, performance specifications apply typically. 3 the time required for the output to cross 0.4 v or 2.4 v. 4 t 14 is derived from the measured time taken by the data outputs to change 0.5 v. the measured number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time, t 14 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
ad7934-6 r e v. a | pa ge 6 o f 2 8 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 4. p a r a me t e r r a t i n g v dd to a g n d /dgnd ?0.3 v to +7 v v drive to a g nd/ dgnd ?0.3 v to v dd +0. 3 v analog i n put v o ltage to a g nd ?0.3 v to v dd + 0.3 v dig i tal i n put v o l t age to dgnd ?0.3 v to +7 v v drive to v dd ?0.3 v to v dd + 0.3 v dig i tal o utput v o ltage t o dgnd ? 0 . 3 v t o v drive + 0.3 v v ref i n t o a g nd ?0.3 v t o v dd + 0.3 v a g nd t o dg nd ?0.3 v t o +0.3 v i n put c u rr en t t o an y p i n ex c e pt supplies 1 10 ma o p era t ing t e mp er a tur e r a nge c o mme r c ia l (b v e rsion) ?40c to +85c stor age t e mpera tur e r a nge ?65c to +150c junc tion t e mpe r a tur e 150c ja ther mal i m pedanc e 97.9c/w ( t sso p) jc ther mal i m pedanc e 14c/w ( t ssop) l e ad t e mper a tur e , s o lder ing r e flo w t e mperatur e (10 sec to 3 0 sec) 255c e s d 1 . 5 k v 1 transient currents of up to 100 ma do not cause s c r latch-up. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (elec t r o static dischar g e) sensitiv e devic e . elec tr osta tic char ges as high as 4000 v r e adily ac cumula te on the human body and t e st e q uipmen t and can dischar g e without det e c t ion. although this pr oduc t f e a tur es pr o p r i etar y esd pr otec ti on ci r c uitr y , per m anen t dama ge may oc cur on dev i c e s subjec ted to high energy elec tr o s ta tic di scharge s . theref or e , p r oper esd pr ec autions a r e r e com m ended to av oid per f or man c e degrada t ion or l o ss of func tiona l it y .
ad7934-6 r e v. a | pa ge 7 o f 2 8 pin conf igura t ion and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 w/b db0 db1 db4 db3 db2 v dd v in 2 v in 1 v in 0 cs agnd v refin /v refout db5 db6 db7 db9 dgnd v drive rd wr convst db10 db8/hben db11 busy clkin v in 3 ad7934-6 top view (not to scale) 04752 -006 figure 2. pin c o nfiguration ta ble 5. pi n f u nct i on d e s c ri pt i o n p i n no . m n emonic description 1 v dd p o w e r supply i n put. t h e v dd r a nge f o r the ad79 34-6 is fr om 2.7 v to 5.25 v . the supply should be dec o upled to a g nd with a 0.1 f capacitor and a 10 f tan t alum capacitor . 2 w/ b w o r d / b yt e i n put. w h en this input is log i c high, w o r d tr an s f er mode is enabl e d , and da ta is tr ansf err e d t o and fr om the ad7934-6 in 12-bit w o r d s on p i n db0 to p i n db11. w h en w/ b is logic low , b y te transf er mod e is enabled . da ta a n d the channel i d ar e tr ansf er r e d on p i n db0 t o p i n db7, and p i n db8/hben assumes its hben func tionalit y . w h en oper a ting in b y t e tr ansf er mode , unused d a ta lines shou ld be tied off t o d g nd . 3 to 10 db0 to db7 da ta bits 0 to 7. thr e e - st a t e para llel d i gital i/ o pi ns tha t pro v id e the c o n v ersi on result, and allow the c o n t rol r e gister to be p r ogrammed . the s e pins ar e con t rolled b y cs , rd , and wr . the logic high/ l o w v o ltage le v e l s f o r these pins ar e d e ter mined b y th e v drive input. 11 v drive l o gic p o w e r su p p ly i n put. the v o ltage sup p lie d a t this pin deter mines wh a t v o ltage the parallel in ter f ac e of the ad7934-6 o p er a t e s . this pi n should be dec o upled to dgn d . the v o ltage a t t h is pin can be di ff er en t to tha t at v dd , but should nev e r ex c eed v dd b y mor e than 0.3 v . 12 dgnd dig i tal gr ound . this is the g r ou nd r e f e r e nc e poi n t f o r all dig i tal cir c uitr y on the ad7934-6. this pin shou ld c o nnec t to the dgnd plane of a system. the dgnd and a g nd v o ltage s shou ld id eally be a t the same pot en tial , and must not be mor e than 0.3 v apar t, ev en on a transie n t basi s . 13 db8/hben da ta bit 8/h i gh byt e enable . w h en w/ b is high, this pin ac ts as data bi t 8, a thr e e - sta t e i/ o pin that is co nt ro l l e d by cs , rd , and wr . w h en w/ b is lo w , this pin ac ts as the high b y t e enable pin. w h en hben is lo w , the lo w b y te of da ta wr itten to or r e ad fr om the ad7934- 6 is on db0 to db7. w h en hben is high, the top f o ur bits of the da ta being wr itten to or r e ad fr om the ad 7934-6 ar e on db0 to db3. w h en r e ading fr om the devic e , db4 and db5 of the high b y t e c o n t ain the id of the ch ann e l c o r r esponding to th e c o n v ersi on r e sult (see the channe l addr es s bits in t a ble 9). db6 and db7 are alwa ys 0. when wr iting to the devic e , db4 to db7 of the high b y te must all be 0s . 14 to 16 db9 to db11 da ta bits 9 to 11. thr e e - sta t e p a ralle l d i gital i/o p i ns tha t pro v id e the c o n v ersio n result and allow the c o n t r o l r e gister to be p r ogr a mmed in w o r d mode . these pins a r e c o n t r o lled b y cs , rd , and wr . the log i c high/lo w v o ltage lev e ls f o r these pins a r e deter mined b y the v drive input. 17 busy busy o utput. l o g i c output indic a ting the sta tus of th e c o n v e r sio n . the busy output goes high f o llo wing the falling edge of c o nvst and sta y s high f o r the dur a tion of the c o n v e r s i o n . o n ce t h e co nv e r s i o n i s c o m p l e te and the r e sult is a v ailable in the output r e g i st er , the bu sy output goes lo w . t h e tr ack - and-hold r e turns t o tr ack mode just prior t o the falling edge of busy , on the 13 th rising edge of sclk (see f i gur e 34). 18 clkin m a ster clock i n put. the clock s o ur c e f o r the c o n v er sion p r oc ess is applied to this pi n. c o n v ersio n time f o r the ad7934-6 takes 13 clock c y cles + t 2 . the fr equenc y of the master clock i n put ther ef o r e deter mines the c o n v ersi on time and achievable thr o ughput r a te . the cl kin sign al can b e a c o n t inuous or burst clock . 19 c o nvst c o n v ersion star t i n put. a falling edge on c o nvst is used to initia te a c o n v er sion. the track - and-hold goes fr om tr ack t o hold mode on the falling edge of c o nvst , and the c o n v e r s i on proc e ss is ini t ia ted a t this poi n t . f o llo w i n g pow e r - d o w n, when o p er a t ing in the autosh ut do w n or aut o s t andb y mode , a ris i ng edge on c o nvst is used to po w e r up the devic e . 20 wr w r it e i n put. a c ti v e low log i c input used in c o nj unc t ion with cs to wr ite d a ta to the c o n t rol r e giste r .
ad7934-6 rev. a | page 8 of 28 pin no. mnemonic description 21 rd read input. active low logic input used in conjunction with cs to access the conversion result. the conversion result is placed on the data bus following the falling edge of rd read while cs is low. 22 cs chip select. active low logic input used in conjunction with rd and wr to read conversion data or write data to the control register. 23 agnd analog ground. this is the ground reference point for all analog circuitry on the ad7934-6. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and mu st not be more than 0.3 v apart, even on a transient basis. 24 v refin /v refout reference input/output. this pin is connected to the in ternal reference, and is the reference source for the adc. the nominal internal reference voltage is 2.5 v, and it appears at this pin. it is recommended that this pin be decoupled to agnd with a 470 nf capacitor. this pin can be overdriven by an external reference. the input voltage range for the external reference is 0.1 v to v dd ; however, care must be taken to ensure that the analog input range does not exceed v dd + 0.3 v. see the reference section. 25 to 28 v in 0 to v in 3 analog input 0 to analog input 3. fo ur analog input channels that are mu ltiplexed into the on-chip track-and- hold. the analog inputs can be programmed to be four si ngle-ended inputs, two fully differential pairs, or two pseudo differential pairs by setting the mode bits in the control register appropriately (see table 9). the analog input channel to be converted can be selected either by writing to the address bits (add1 and add0) in the control register prior to the conversion, or by using the on-chip sequencer. the input range for all input channels can be either 0 v to v ref , or 0 v to 2 v ref , and the coding can be binary or twos complement, depending on the states of the range and coding bits in the control register. any unused input channels should be connected to agnd to avoid noise pickup.
ad7934-6 rev. a | page 9 of 28 terminology integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 000) to (00 001) from the ideal (that is, agnd + 1 lsb). offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 110) to (111 111) from the ideal (that is, v ref C 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero-code error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the midscale transition (all 0s to all 1s) from the ideal v in voltage (that is, v ref ). zero-code error match this is the difference in zero-code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the last code transition (011 110) to (011 111) from the ideal (that is, +v ref C 1 lsb) after the zero-code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100 000) to (100 001) from the ideal (that is, ?v ref + 1 lsb) after the zero-code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation this is a measure of the level of crosstalk between channels. it is measured by applying a full-scale sine wave signal to the three, nonselected input channels and applying a 50 khz signal to the selected channel. the channel-to-channel isolation is defined as the ratio of the power of the 50 khz signal on the selected channel to the power of the noise signal on the unse- lected channels that appears in the fast fourier transform (fft) of this channel. the noise frequency on the unselected channels varies from 40 khz to 740 khz. the noise amplitude is at 2 v ref , while the signal amplitude is at 1 v ref . see figure 4. power supply rejection ratio (psrr) psrr is defined as the ratio of the power in the adc output at full-scale frequency ( f ) to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of the noise varies from 1 khz to 1 mhz. psrr (db) = 10log(pf / pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency ( f ) to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in? of frequency f s . cmrr (db) = 10log( pf/pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output.
ad7934-6 rev. a | page 10 of 28 t r a c k-a nd-h o l d a c q u i s iti o n t i m e the t r ack - an d - h o ld am plif ier r e t u r n s t o t r ack m o de a t t h e e n d o f co n v ersio n . t h e t r ack-and- h o ld acq u isi t io n t i m e is t h e t i m e r e q u ir e d fo r t h e o u t p u t o f t h e t r ack-and- h o ld am plif ier t o r e a c h i t s f i n a l val u e , wi t h in ? ls b , a f t e r t h e en d o f co n v er sio n . si g n a l - t o - n o i s e a n d d i s t or t i on r a t i o ( s i n a d ) this is t h e m e a s ur e d ra t i o o f sig n a l -t o- n o is e and dist o r t i o n a t t h e ou t p u t o f t h e ad c. th e sig n al is t h e r m s am pli t ude o f t h e f u ndam e n t a l . n o is e is t h e su m o f a l l n o nf u ndam e n t a l sig n a l s up t o half the s a m p lin g f r e q uen c y (f s /2), excl udi n g dc. th e ra t i o is d e pe n d e n t o n th e n u m b e r o f q u a n ti z a t i o n l e v e l s i n th e d i gi ti z a - t i o n p r o c es s; t h e m o r e le ve ls, t h e smal ler t h e q u a n t i za t i o n n o is e. t h e t h eo r e tical s i n a d ra tio f o r a n ideal n-b i t co n v er t e r wi t h a s i ne w a ve i n put i s g i ve n b y : sinad = (6.02 n + 1.76) db th us, f o r a 12-b i t con v er t e r , s i n a d is 74 db . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h d i s th e ra tio o f th e rm s s u m o f h a rm o n i c s t o th e f u ndam e n t al . f o r th e ad7934-6, i t is def i n e d as: () 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 20log db + + + + ? = w h er e : v 1 is t h e r m s am pli t ude o f t h e f u ndam e n t al . v 2 , v 3 , v 4 , v 5 , and v 6 a r e t h e r m s a m pl i t u d es o f t h e s e co nd t h r o ug h t h e s i x t h ha r m o n ics. p e a k h a rmo n i c o r s p uri o us n o is e this is def i n e d as t h e ra t i o o f t h e r m s val u e o f t h e n e xt la rg es t co m p o n en t in t h e a d c o u t p u t s p ectr um (u p t o f s /2 an d excl udin g dc) t o t h e r m s val u e of t h e f u ndam e n t al . n o r m al l y , t h e va l u e o f t h is sp e c if ic a t ion is det e r m i n e d b y t h e la rgest ha r m o n ic in t h e s p e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ics a r e b u r i e d in t h e n o is e f l o o r , i t is a n o i s e p e ak. inte r m o d u l at i o n d i s t or t i on w i t h i n put s c o n s i s t i ng of s i ne w a ve s a t t w o f r e q u e nc i e s , f a a n d fb , a n y a c ti v e d e v i ce wi t h n o nlin ea ri ti e s cr ea t e s d i s t o r ti o n p r o d uc ts a t s u m a nd dif f er en ce f r e q uen c ies o f mfa nf b , w h ere m, n = 0, 1, 2, 3, a nd s o o n . i n te r m o d u l a t io n disto r t i o n ter m s a r e th ose f o r whic h n e i t h e r m n o r n a r e eq ual to zer o . f o r exa m p l e , t h e s e co nd-o r der t e r m s in c l ude (fa + fb) a n d (f a ? fb), w h i l e t h e t h ird- o r der t e r m s i n cl ude (2fa + fb), ( 2 fa ? fb), (fa + 2fb), a nd (fa ? 2 f b). the ad7934 -6 is t e s t e d usin g t h e ccif s t andar d w h er e tw o in p u t f r e q uen c ies n e a r t h e t o p end o f t h e i n p u t b a ndwid t h a r e us e d . i n t h is cas e , t h e s e cond-o r der ter m s a r e usua l l y dist ance d in f r e q ue n c y f r o m t h e o r ig in a l sine w a v e s, w h i l e t h e t h ir d - o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o the in p u t f r eq uen c ies. a s a r e su lt, t h e s e co nd- and t h i r d-o r der ter m s a r e sp e c if ie d s e p a ra te ly . t h e ca lc u l a t io n o f t h e in t e r m o d u l a t io n di st o r t i o n is as p e r t h e thd s p e c if ic a t ion, w h er e i t is t h e ra t i o o f t h e r m s su m of t h e i n d i v i d u a l d i s t or t i on pro d u c t s to t h e r m s am pl itu d e o f t h e s u m o f t h e f u ndam e n t als, exp r es s e d i n dbs.
ad7934-6 rev. a | page 11 of 28 typical perf orm ance cha r acte ristics t a = 2 5 c , u n l e ss ot he r w i s e no t e d. supply ripple frequency (khz) pssr ( d b ) ?60 ?70 ?80 ?90 ? 110 ? 100 ? 120 10 210 610 410 810 1010 04752-007 100mv p-p sine wave on v dd and/or v drive no decoupling differential/single-ended mode int ref ext ref figure 3. psrr vs. s u pply ripple f r eq uency wi tho u t supp l y deco up l i ng noise frequency (khz) nois e is olation (db) ?70 ?75 ?90 ?85 ?80 ? 195 0 100 400 200 300 600 500 800 700 04752-021 internal/external reference v dd = 5v figure 4. channe l- to-channe l isolat ion frequency (khz) s i nad (db) 80 70 60 50 30 40 20 0 100 400 200 300 600 500 1000 700 800 900 04752-008 f sample = 625ksps range = 0 to v ref differential mode v dd = 5v v dd = 3v fig u re 5. sina d v s . a n al og input f r eq uency f o r v a r i ous s u pply v o lt ag es frequency (khz) ??? 0 ?10 ?20 ?50 ?40 ?30 ?90 ? 100 ?80 ?70 ?60 ? 110 0 100 200 300 400 500 600 700 04752-009 4096 point fft v dd = 5v f sample = 625ksps f in = 49.62khz sinad = 70.94db thd = ? 90.09db differential mode amp l itude (db) figure 6. fft @ v dd = 5 v code dnl e rror (ls b ) 1.0 0.8 0.6 0.4 0.2 ? 0.2 0 ? 0.8 ? 0.6 ? 0.4 ? 1.0 0 500 2000 1000 1500 3000 2500 4000 3500 04752 -010 v dd = 5v differential mode figure 7. typical d n l @ v dd = 5 v code in l er r o r ( l sb ) 1.0 0.8 0.6 0.4 0.2 ? 0.2 0 ? 0.8 ? 0.6 ? 0.4 ? 1.0 0 500 2000 1000 1500 3000 2500 4000 3500 04752-011 v dd = 5v differential mode figure 8. typical in l @ v dd = 5 v
ad7934-6 rev. a | page 12 of 28 v ref (v) dnl (ls b ) 4 3 1 2 0 ?1 0.25 0.50 1.25 0.75 1.00 2.00 1.75 1.50 2.75 2.50 2.25 04752-012 single-ended mode positive dnl negative dnl figure 9. dnl vs. v re f fo r v dd = 3 v v ref (v) e ffe ctiv e numbe r of bits 12 11 10 8 9 7 6 0 0.5 1.5 1.0 2.5 2.0 4.0 3.5 3.0 04752-013 v dd = 5v differential mode v dd = 5v single-ended mode v dd = 3v single-ended mode v dd = 3v differential mode figure 10. enob vs. v ref v ref (v) offset ( l sb ) 0 ? 0.5 ? 1.5 ? 1.0 ? 3.5 ? 3.0 ? 2.5 ? 2.0 ? 4.0 ? 4.5 ? 5.0 0 0.5 1.5 1.0 2.5 2.0 3.5 3.0 04752-014 single-ended mode v dd = 5v v dd = 3v figure 11. offset vs. v ref code ??? 10000 9000 7000 8000 3000 4000 5000 6000 2000 1000 0 2046 2047 2048 2049 2050 04752-015 differential mode 3 codes internal ref 9997 codes fi gur e 12 . h i sto g r a m o f co d e s fo r 10 k sam p les @ v dd = 5 v wi th the internal r e ference ripple frequency (khz) cmrr (db) ?60 ?70 ?80 ? 100 ?90 ? 110 ? 120 0 200 400 800 600 1200 1000 04752-017 differential mode figure 13. cmrr vs. input freq uen c y w i th v dd = 5 v and 3 v
ad7934-6 rev. a | page 13 of 28 control register the control register on the ad7934-6 is a 12-bit, write-only register. data is written to this register using the cs and wr pins. the control register is shown in table 6 and the functions of the bits are described in table 7. at power-up, the default bit setti ngs in the control register are all 0s. table 6. control register bits msb lsb db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 pm1 pm0 coding ref zero add1 add0 mode1 mode0 seq1 seq0 range table 7. control register bit function description bit no. mnemonic description 11, 10 pm1, pm0 power management bits used to select the power mode of operation. the user can choose between normal mode and various power-down modes of operation as shown in table 8. 9 coding selects the output coding of the conversion result. if set to 0, the output coding is straight (natural) binary. if set to 1, the output coding is twos complement. 8 ref selects whether the internal or external reference is used to perform the conversion. if this bit is logic 0, an external reference should be applied to the v ref pin. if this bit is logic 1, the internal reference is selected. see the reference section. 7 zero not used. this bit should always be set to logic 0. 6, 5 add1, add0 two address bits that either select which analog input ch annel is to be converted in the next conversion, if the sequencer is not used, or select the final channel in a consecutive sequence when the sequencer is used as described in table 10. the selected input channel is decoded as shown in table 9. 4, 3 mode1, mode0 two mode pins that select the type of analog input on the four v in pins. the ad7934-6 has four single-ended inputs, two fully differential inputs, or tw o pseudo differential inputs. see table 9. 2 seq1 used in conjunction with the seq0 bit to control the sequencer function. see table 10. 1 seq0 used in conjunction with the seq1 bit to control the sequencer function. see table 10. 0 range selects the analog input range of the ad7934-6. if set to 0, the analog input range extends from 0 v to v ref . if it is set to 1, the analog input range extends from 0 v to 2 v ref . when this range is selected, av dd must be 4.75 v to 5.25 v if a 2.5 v reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. see the analog input conf igurations section for more information. table 8. power mode selection using the power management bits in the control register pm1 pm0 mode description 0 0 normal mode when operating in normal mode, all circuitry is fully powered up at all times. 0 1 autoshutdown when operating in autoshutdown mode, the ad7934-6 enters full shutdown mode at the end of each conversion. in this mode, all circuitry is powered down. 1 0 autostandby when the ad7934-6 enters this mode, the reference remain s fully powered, the reference buffer is partially powered down, and all other circuitry is fully powered down. this mode is simila r to autoshutdown mode, but it allows the part to power-up in 7 s (or 600 ns if an external reference is used). see the power modes of operation section for more information. 1 1 full shutdown when the ad7934-6 enters this mode, all circuitry is po wered down. the information in the control register is retained. table 9. analog input type selection mode0 = 0, mode1 = 0 mode0 = 0, mode1 = 1 mode0 = 1, mode1 = 0 mode0 = 1, mode1 = 1 channel address four single-ended i/p channels two fully differential i/p channels two pseudo differential i/p channels not used add1 add0 v in+ v in? v in+ v in? v in+ v in? 0 0 vin0 agnd vin0 vin1 vin0 vin1 0 1 vin1 agnd vin1 vin0 vin1 vin0 1 0 vin2 agnd vin2 vin3 vin2 vin3 1 1 vin3 agnd vin3 vin2 vin3 vin2
ad7934-6 rev. a | page 14 of 28 sequencer operation the configuration of the seq0 and seq1 bits in the control register allow the user to use the sequencer function. table 10 outl ines the two sequencer modes of operation. table 10. sequence selection modes seq0 seq1 sequence type 0 0 this configuration is selected when the sequence function is not used. the analog input channel selected on each individual conversion is determined by the contents of th e channel address bits, add1 and add0, in each prior write operation. this mode of operation reflects the normal operati on of a multichannel adc, without the sequencer function being used, where each write to the ad7934-6 selects the next channel for conversion. 0 1 not used. 1 0 not used. 1 1 this configuration is used in conjunction with the chan nel address bits, add1 and add0, to program continuous conversions on a consecutive sequence of channels from channel 0 to a selected final channel, as determined by the channel address bits in the control register. when in differential or pseudo-differential mode, inverse channels (for example, vin1, vin0) are not converted in this mode. note on writing to the control register to program the sequencer the ad7933 and ad7934 need 13 full clkin periods to perform a conversion. if the adc does not receive the full 13 clkin periods , the conversion is aborted. if a conversion is aborted after appl ying 12.5 clkin periods to the adc, ensure that a rising edge o f convst or a falling edge of clkin is applied to the part before writing to the control register to program the sequencer. if these con ditions are not met, then the sequencer is not in the correct state to handle being reprogrammed for another sequence of conversions. as a resu lt, the performance of the converter is not guaranteed.
ad7934-6 rev. a | page 15 of 28 circuit i n forma t ion the ad7934 -6 is a fas t , 4-c h a n ne l , 12-b i t, sin g l e -s u p p l y , successi v e a p p r o x ima t ion a n a l og-t o-d i g i t a l co n v er t e r . the p a r t o p era t es f r o m a 2.7 v t o 5.25 v p o w e r s u p p l y a nd f e a t ur es thr o ug h p u t r a t e s u p t o 625 ks ps. the ad7934 -6 p r o v ides t h e us er wi t h an o n -chi p trac k-an d- h o ld , an acc u ra te in t e r n a l r e fer e n c e, a n a n a l og-to-dig i t a l c o n v e r te r , a n d a p a r a l l el i n te r f a c e hou s e d i n a 2 8 - l e a d t s s o p pa c k a g e . the ad7934 -6 has f o ur a n alog in p u t c h a n ne ls t h a t can be co nf igur e d to b e fo ur sin g le-e nde d i n p u ts, tw o f u l l y dif f er en t i a l p a irs o r tw o ps e u do dif f er en t i a l p a irs. an o n -ch i p cha n nel s e q u e n cer al lo w s t h e us er t o s e l e c t a co ns e c u t i v e s e q u e n ce o f channel s t h rou g h w h ich t h e ad c c a n c y cl e w i t h e a ch f a l l i n g ed g e o f co n v s t . the a n alog in p u t ra n g e f o r th e ad7934-6 is 0 to v ref or 0 to 2 v ref , de p e ndin g on t h e st a t us o f t h e r a n g e b i t in t h e co n t r o l r e g i s t er . the o u t p u t co din g o f t h e ad c ca n b e e i t h er st r a ig h t b i na r y o r tw o s co m p le m e n t , dep e ndi ng o n t h e st a t us o f t h e c o di ng bit i n t h e c o n t ro l re g i ste r . the ad7934 -6 p r o v ides f l exi b l e p o w e r ma na gem e n t o p t i o n s to al lo w us ers t o achie v e t h e b e s t p o w e r p e r f o r ma n c e fo r a g i v e n t h rou g h p ut r a te . t h e s e opt i ons are s e l e c t e d b y pro g r a m m i ng th e p o w e r ma nag e m e n t b i ts, p m 1 a nd pm0, in t h e co n t r o l re g i ste r . converter operation the ad7934 -6 is a s u cces si ve a p p r o x ima t ion ad c bas e d o n t w o ca pa ci ti v e di gi tal- t o - a nalog co n v e r t e r s (d a c s). f i gur e 14 a nd f i gur e 15 sh o w sim p l i f i e d s c h e ma tic s o f the ad c in acq u isi t ion an d co n v ersio n pha s e , r e sp e c t i ve ly . the ad c co m p r i s e s co n t rol log i c, sar , and tw o ca p a c i tiv e d a cs. b o th f i gur e s s h o w t h e o p era t ion o f t h e ad c i n dif f er en t i al/ps e udo dif f er en t i a l m o de. si n g le- e n d e d m o de op er a t i o n is simi la r b u t v in? is in t e r n al ly tied t o a g nd . i n t h e acq u isi t io n p h as e , s w 3 is clos e d , sw1 and sw2 a r e in p o si t i o n a, t h e c o m p a r a t o r is h e l d i n a b a l a nc e d c o nd i t i o n , a n d t h e s a m p l i ng c a p a c i tor ar r a y s acq u ir e t h e dif f er en t i al sig n al on t h e i n p u t. 04752-023 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a fig u re 1 4 . a d c a c q u is it i o n ph as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 15), sw3 o p e n s, and sw1 an d s w 2 m o ve t o p o si tion b , c a usin g t h e co m p a r a t o r t o b e com e u n b a lan c e d . b o t h i n p u ts a r e dis c o n ne c t e d on ce t h e co n v ersio n b e g i n s . th e con t r o l log i c a n d cha r ge r e dis t r i b u t i o n d a cs a r e us e d to add an d sub t r a c t f i xe d am o u n t s o f cha r ge f r o m th e sam p lin g ca p a ci t o r a r ra ys t o b r in g t h e co m p a r a t o r b a ck i n to a b a l a nc e d c o nd i t i o n . whe n t h e c o m p ar a t or i s r e balan c e d , t h e co n v ersio n is com p let e . th e con t r o l log i c g e n e ra t e s t h e ou t p ut co de o f t h e ad c. th e o u t p u t im p e dan c es o f t h e s o ur ces dr i v i n g t h e v in+ and t h e v in ? pi n s m u s t m a tc h ; o t h e r w is e , t h e t w o in p u ts ha ve dif f er en t s e t t l i ng t i m e s, re su lt i n g i n e r ror s . 04752-024 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a fi gur e 15 . adc co nve r si on pha s e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad7 934-6 is ei t h er stra ig h t b i na r y o r tw o s co m p le m e n t , dep e ndi n g on t h e st a t us o f t h e c o din g b i t in t h e con t r o l r e g i s t er . th e desig n e d co de t r a n si t i o n s o c c u r a t s u cces si v e ls b val u es (t ha t is, 1 ls b , 2 ls bs, and s o o n ), an d t h e ls b size is v ref /4096. the ideal tra n sf er c h a r ac t e r i s t ics o f the ad7934-6 f o r b o th s t ra ig h t b i na r y a n d tw os c o m p l e m e n t o u t p u t co ding a r e sho w n in f i gure 1 6 and f i gure 17, re s p e c t i v e l y . 04752-025 000...000 111...111 1 lsb = v ref /4096 1 lsb +v ref ? 1 lsb analog input adc code 0v note: v ref is either v ref or 2 v ref 000...001 000...010 111...110 111...000 011...111 fi gur e 16 . ide a l tr ansfe r char ac te ri sti c with str a ight bina ry output co di n g
ad7934-6 rev. a | page 16 of 28 04752 -026 100...000 011...111 1 lsb = 2 v ref /4096 ?v ref + 1 lsb v ref +v ref ? 1 lsb adc code 100...001 100...010 011...110 000...001 000...000 111...111 fi gur e 17 . ide a l tr ansfe r char ac te ri sti c with tw os c o mp le ment o u tput coding and 2 x v ref ra nge typical connection diagram f i gur e 18 sh o w s a typ i cal co nn e c tio n dia g ra m fo r th e ad7934-6. th e a g nd and d g nd p i n s a r e conn ec t e d t o g e t h er a t t h e de vice fo r g o o d n o is e s u p p r es si o n . th e v refin /v refo ut p i n is de co u p led t o a g nd wi th a 0.47 f c a p a c i tor to a v oi d noi s e pi ck up i f t h e i n te r n a l re fe re nc e i s us ed . al t e r n a t i v e l y , v refin /v refo ut ca n be conn e c t e d t o an e x te r n a l re f e re n c e s o u r c e . in t h i s c a s e , t h e re f e re nc e pi n s h o u l d be decou p led wi t h a 0.1 f ca p a ci t o r . i n bo t h cas e s , t h e a n alog in p u t ra n g e can ei t h er b e 0 v t o v ref (ran ge b i t = 0) o r 0 v t o 2 v ref (r an ge b i t = 1). th e a n a l og in p u t co nf igu- r a t i o n is e i t h er fo ur sin g le-e nde d i n p u ts, tw o di f f er en t i a l p a irs o r tw o ps eudo dif f er en t i al p a irs (s e e t a b l e 9). th e v dd pi n co nn e c ts t o ei t h er a 3 v o r 5 v s u p p l y . th e v o l t ag e a p plie d t o th e v dr iv e in p u t co n t r o ls t h e v o l t a g e o f t h e dig i t a l in t e r f ace . h e r e in f i gur e 18 i t is co nn ec t e d t o t h e s a m e 3 v s u p p l y o f th e micr o p r o ces s o r t o al lo w a 3 v lo g i c in ter f ace (s e e the dig i tal inp u t s s e c t i o n ) . 04752 -027 0.1 f1 0 f 3v/5v supply 3v supply c/ p ad7934-6 0.1 f 0.1 f external v ref 0.47 f internal v ref 0 to v ref / 0 to 2 v ref agnd dgnd w/b clkin cs v drive v in 0 v dd v refin /v refout v in 3 10 f 2.5v v ref rd convst wr busy db0 db11/db9 figure 18. typ i c a l c o nne ction d i ag ram analog input struc t ure f i gur e 19 sh o w s th e e q ui valen t cir c ui t o f t h e a n alog in p u t s t r u c t ur e o f th e ad7934-6 in dif f er en tial/ps e udo dif f er en tial m o de. i n si n g le -ende d m o de, v in? i s i n te r n a l l y t i e d to a g nd . the fo ur dio d es p r o v ide es d p r o t e c t i o n fo r t h e a n alog in p u ts. c a r e m u st b e ta k e n t o ens u r e tha t t h e a n alog in p u t sig n als n e v e r exceed t h e s u p p l y ra ils b y m o r e tha n 300 mv . this ca us es t h e dio d e s to b e co m e fo r w a r d- b i a s e d and st a r t cond uc t i ng i n to t h e s u bs tr a t e . th es e dio d es can co nd uc t u p t o 10 ma wi t h o u t ca usin g ir r e v e rsi b le dama ge t o t h e p a r t . the c1 c a p a ci t o rs in f i gur e 19 ar e typ i cal l y 4 pf , a nd can pr i m ar i l y b e att r ibu t e d to pi n c a p a c i t a nc e. t h e re s i s t or s are l u m p e d com p on en ts made u p o f th e o n r e sis t an ce o f t h e swi t ch es. the val u e o f th es e r e sis t o r s is typ i c a l l y a b o u t 100 ?. the c2 c a p a ci t o rs a r e t h e s a m p l i n g c a p a ci t o rs o f t h e ad c and typ i c a l l y ha v e a ca p a ci tan c e o f 4 5 pf . r1 c2 v in + v dd c1 d d 04752 -028 r1 c2 v in ? v dd c1 d d fig u re 1 9 . e q uiv a l e nt a n al og input c i r c uit , co n v er si on ph a s e s w i t ch e s open , tra c k ph ase swit ches c l osed f o r a c a p p l i c a t i o ns , re m o v i ng h i g h f r e q u e nc y c o m p o n e n t s f r o m t h e a n al og in p u t s i g n al is r e co mm en d e d b y t h e use o f a n r c lo w - p a s s f i l t er on t h e r e l e van t an a l o g i n pu t pins . i n a ppl i c a t ions w h ere h a r m on i c d i stor t i on a n d s i g n a l - t o - noi s e r a t i o ar e c r it i c a l , t h e an a l o g i n put s h ou l d b e d r ive n f r om a l o w i m p e d a nc e s o u r c e . l a rg e s o ur ce i m p e dan c es sig n if ica n t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e a d c. this ca n n e ce s s i t a t e t h e us e o f a n i n p u t b u f f er am pl i f i e r . t h e c h oi c e of t h e op am p i s a f u nc t i o n of t h e p a r t i c u l a r ap p l i c at i o n . w h en n o am plif ier is us e d t o dr i v e t h e a n alog i n p u t , t h e s o ur ce im p e dan c e sh ou ld b e l i mi t e d to lo w val u es. the maxi m u m s o ur ce i m p e dance dep e n d s o n t h e am o u n t o f t h d t h a t can b e t o lera t e d . th e thd i n cr e a s e s as t h e s o ur ce i m p e dan c e in cr e a s e s a nd p e r f o r ma n c e deg r ades . f i gu r e 20 a n d f i gure 21 sh o w a g r a p h o f t h e th d vs. s o ur ce im p e dan c e wi t h a 50 khz i n p u t tone for b o t h v dd = 5 v a n d 3 v , in sin g le-en d ed m o de an d dif f er en t i al m o de , r e s p e c t i v e l y .
ad7934-6 rev. a | page 17 of 28 r source ( ? ) thd (db) ?40 ?45 ?50 ?55 ?80 ?75 ?70 ?65 ?60 ?90 ?85 10 100 1k 04752-018 f in = 50khz v dd = 5v v dd = 3v figure 2 0 . t h d v s . sour ce i m ped a n ce in s i ngl e -e nded m o de r source ( ? ) thd (db) ?60 ?80 ?75 ?70 ?65 ? 100 ?85 ?90 ?95 10 100 1k 04752-019 f in = 50khz v dd = 5v v dd = 3v figure 2 1 . t h d v s . sour ce i m ped a n ce in d i ffere ntia l m o d e fi g u r e 2 2 s h ow s a g r ap h o f t h e t h d v s . t h e a n a l o g i n pu t f r eq uen c y f o r v a r i o u s s u p p lies, while s a m p lin g a t 625 kh z wi t h a n scl k o f 10 mh z. i n this cas e , t h e s o ur ce im p e dan c e is 10 ?. input frequency (khz) thd (db) ?50 ?60 ?70 ?80 ? 110 ? 100 ?90 ? 120 0 100 400 200 300 600 500 700 04752-020 f sample = 625ksps range = 0 to v ref v dd = 3v single-ended mode v dd = 5v/3v differential mode v dd = 5v single-ended mode fig u re 2 2 . t h d v s . a n al og input f r eq uency f o r v a r i ous s u pply v o lt ag es analog input c o nfig urations the ad7934 -6 has s o f t wa r e s e l e c t a b le a n alog in p u t co nf igura t io n s . the us er can cho o s e ei t h er fo ur sin g le- ende d in pu ts, t w o f u l l y dif f er en t i a l p a irs, o r t w o ps eudo d i f f e r e n t i a l p a irs. t h e a n a l og i n p u t c o nf igur a t ion i s ch os e n b y s e t t in g t h e mo d e 0/ m o d e 1 b i ts in t h e in t e rnal co n t r o l r e gis t e r (s ee t a b l e 9 ) . single-ended mode the ad7934 -6 ca n ha v e f o ur sin g le-ended a n al og in p u t cha nnels b y s e t t in g t h e mode0 a nd mode1 b i ts in t h e co n t r o l r e g i s t er t o 0. i n a p plic a t io n s w h er e t h e s i g n al s o ur ce has a hi g h im p e dan c e, i t is r e co mm e nde d to b u f f er t h e a n a l o g in p u t b e fo r e a p p l ying i t t o the ad c. an o p am p s u i t a b le f o r this f u n c t i o n is th e ad8021. the a n alog in p u t r a n g e o f the ad7934-6 ca n be p r og ra mm ed t o be ei t h er 0 t o v ref o r 0 t o 2 v ref . i f th e a n alog in p u t si gn al t o be sa m p led i s b i po la r , th e i n t e rn al r e fer e n c e o f t h e ad c can b e us e d t o ext e r n al l y b i as u p t h is sig n a l to ma ke it t h e c o r r e c t fo r m a t fo r t h e ad c. f i gur e 23 sh o w s a typ i cal co nn e c tio n dia g ra m when op era t in g t h e ad c in si ng le-e n d e d m o d e . this d i a g ram sho w s a b i p o la r s i g n a l of am pl itu d e 1 . 2 5 v b e i n g pre c on d i t i on e d b e f o re it i s a p p l ie d t o t h e ad7934-6. i n cas e s wher e t h e a n alog in p u t a m p l i t ude is 2.5 v , t h e 3r r e sist o r ca n be r e p l aced wi t h a r e sis t o r o f val u e r . th e r e s u l t an t v o l t a g e on t h e a n alog in p u t o f th e ad7934-6 is a sig n al ra n g ing f r o m 0 v t o 5 v . i n this cas e , th e 2 v ref m o de can b e us e d . 0.47 f +1.25v v in r r r 3r 0v ?1.25v +2.5v 0v v in0 v in7 v refout ad7934-6 1 1 additional pins omitted for clarity. 04752-031 figure 23. s i ngle-ended mod e c o nne ction diagr a m differenti a l m o de the ad7934 -6 ca n ha v e tw o dif f er en tial a n alo g in p u t p a irs b y s e t t in g t h e m o d e 0 a n d m o de1 b i ts in t h e con t r o l r e g i s t er t o 0 a nd 1, r e s p ec t i v e l y . dif f er en t i al s i g n als ha v e s o me b e n e f i ts o v er si n g le-e nde d si gn als, in c l udin g n o ise im m u n i t y ba sed o n t h e d e v i ce s co mm on- m o d e r e j e c t io n, and i m p r o v e m e n ts i n disto r t i o n p e r f o r ma n c e . f i gur e 24 def i n e s t h e f u l l y dif f er en t i al a n alog in p u t o f the ad7934-6.
ad7934-6 rev. a | page 18 of 28 04752-032 v ref p-p v in+ v in? v ref p-p *additional pins omitted for clarity ad7934-6* common-mode voltage fi gure 24 . di fferent i a l input defi ni tio n the am pl i t u d e of t h e dif f er e n t i al sig n a l i s t h e dif f er e n ce b e t w e e n th e si gnal s a p p l ied t o th e v in+ and v in ? p i n s in eac h di f f e r en t i al p a ir (t h a t is , v in + ? v in ? ). v in + and v in ? s h o u ld be sim u l t a n e o u s l y dr i v en b y tw o sig n als, e a c h o f am p l i t ude v ref (o r 2 v ref de p e nding on t h e ran g e chos e n ), w h i c h a r e 1 8 0 o u t o f phas e . the am pl i t u d e of t h e dif f er e n t i al sig n a l i s t h erefo r e ? v ref to + v re f peak -t o-peak (th a t is , 2 v re f ), r e ga rdl e ss o f t h e comm on mo de (cm) . the c o mmo n mo de is t h e a ver a g e o f t h e t w o s i g n als , (v in + + v in ? ) / 2 , and i s t h erefo r e t h e v o l t a g e on w h i c h t h e t w o i n pu t s a r e ce n t ere d . this r e su l t s i n t h e s p an of e a ch i n p u t b e ing cm v ref /2. this v o l t a g e m u s t b e s e t u p ex t e r n al ly , and i t s ra n g e va r i e s w i t h t h e r e fer e nce v a l u e v re f . a s t h e val u e o f v ref in cr eases , t h e co mm o n -m ode ra n g e decr eases . w h en d r i v i n g t h e i n pu t s w i t h an am plif ier , t h e a c t u a l co m m on - m o d e r a n g e is d e t e rmin e d b y t h e a m p l i f ie r s o u t p u t v o l t a g e swin g. f i gur e 25 an d f i gur e 26 sh o w ho w t h e co mm on-m o d e ra n g e typ i c a l l y va r i es wi t h v ref f o r a 5 v p o w e r s u p p l y usin g th e 0 t o v ref ra n g e o r 0 t o 2 v ref r a nge, re sp e c t i v e ly . t h e c o m m on m o de m u s t b e i n t h is ra n g e t o gua r a n t e e t h e f u n c t i o n ali t y o f t h e ad7934-6. w h en a con v ers i o n t a k e s place , t h e co mm o n mo de is r e je c t e d . t h i s r e s u l t s in a v i r t uall y n o ise - f r ee si gn al o f a m p l i t ud e ?v ref to + v ref , co r r es p o ndin g t o t h e dig i tal co des 0 to 4096. i f th e 0 to 2 v ref ra n g e i s us e d , t h e n t h e in p u t sig n al am pli t ude ext e n d s fr o m ? 2 v ref t o +2 v ref . v ref (v) common-mode range (v ) 3.5 3.0 2.0 1.5 2.5 1.0 0.5 0 0 0.5 1.5 1.0 2.0 2.5 3.0 04752-033 t a = 25 c fig u re 2 5 . inp u t co mm on-m ode r a ng e v s . v ref ( 0 to v ref ra n g e , v dd = 5 v) v ref (v) common-mode range (v ) 4.5 4.0 3.0 1.5 2.0 2.5 3.5 1.0 0.5 0 0.1 0.6 1.6 1.1 2.1 2.6 04752-034 t a = 25 c fig u re 2 6 . inp u t co mm on-m ode r a ng e v s . v ref (2 v ref ra n g e , v dd = 5 v) driving differential inputs dif f er en t i al op e r a t io n r e q u ir es t h a t v in + an d v in ? be sim u l t an eo us l y dr i v en wi t h tw o eq ual sig n als tha t a r e 180 o u t o f p h as e . th e c o mm on m o de m u s t be s e t u p ext e r n al l y a n d has a ra n g e t h a t is d e t e r m i n e d b y v ref , t h e p o w e r su p p l y , a nd t h e p a r t ic u l a r a m pli f ier us e d t o dr i v e t h e a n alog i n pu ts. dif f er en t i al m o des o f o p era t io n wi t h ei t h er a n ac o r a dc i n p u t p r o v ide t h e b e st t h d p e r f or m a nc e ove r a w i d e f r e q u e nc y r a nge. n o t a l l a p p l i c a t i o n s ha ve a si gn al p r eco n d i ti o n e d f o r d i f f er en ti al o p er a t ion, s o t h er e is o f ten a n e e d to p e r f o r m si n g le-e nde d - to - dif f er en t i al con v ersio n . using an op a m p p a ir an o p a m p p a ir ca n be us e d t o dir e c t l y co u p le a dif f er en t i al sig n al t o o n e o f th e analog in p u t p a irs o f th e ad7934-6. th e cir c ui t co nf igur a t io n s s h o w n in f i gur e 27 a nd f i gur e 28 sh o w h o w a d u a l o p a m p can b e us ed t o co n v er t a sing le-en d e d sig n a l in t o a dif f er en t i al sig n al fo r b o t h a b i p o la r a nd uni p ol a r in pu t s i g n a l , re sp e c t i v e ly . the v o l t a g e a p plie d t o p o i n t a s e ts u p t h e co mm o n - m o d e vol t a g e. i n b o t h di a g r a m s , i t is c o nn e c te d in s o m e wa y to t h e r e fer e n c e , b u t an y val u e in t h e co mm on- m o d e ra n g e ca n b e in p u t h e r e t o s e t u p the co mm on m o de . a s u i t ab le d u al o p am p fo r us e in t h is c o nf igura t io n t o p r o v id e d i f f er en t i a l dr i v e t o t h e ad7934-6 is t h e ad8022. i t is ad vis a b l e t o t a k e ca r e w h en ch o o sin g t h e o p a m p; t h e s e le c t ion d e p e nds o n t h e r e q u ir e d p o wer su p p ly a n d sy ste m p e r f o r ma n c e ob je c t i v es. the dr iv er cir c ui ts in f i gur e 27 a nd f i gur e 28 a r e o p t i mi ze d fo r dc co u p lin g a p plic a t io n s r e q u ir i n g b e st d i s t or t i on p e r f or m a nc e. t h e c i rc u i t c o n f i g u r a t i o n i n f i gur e 27 co n v e r ts a n d l e vel shi f ts a sin g l e -e n d e d , g r o u nd- r e f e r e n c ed , b i pola r si gn al t o a d i f f er en ti al si gn al cen t er e d a t th e v ref le vel o f t h e ad c. t h e cir c ui t co nf igur a t io n sh o w n in f i gur e 28 co n v e r ts a uni p o l a r , si n g le-e nde d sig n a l in to a dif f er en t i al sig n al .
ad7934-6 rev. a | page 19 of 28 220 ? 10k ? 2 v ref p-p gnd 440 ? 220 ? 220 ? 20k ? 220 ? 27 ? 27 ? v+ v? v+ v? a v in+ v in? v ref ad7934-6 0.47 f 04752-035 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v fi gure 27 . dual op am p circui t to c o nvert a si ng l e -ended bi p o la r si gna l int o a d i f f e r e nt i a l u n ipo l a r s i g n a l 10k ? v ref p-p v ref gnd 440 ? 220 ? 220 ? 220 ? 27 ? 27 ? v+ v? v+ v? a v in+ v in? v ref ad7934-6 0.47 f 04752-036 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v fi gur e 28 . dual op am p cir c ui t to co nve r t a si ng l e -ende d uni p ol ar si gnal int o a d i f f e r e nt i a l s i g n a l an o t h e r m e t h o d o f dr ivin g t h e ad7934-6 is t o us e the ad8138 dif f er en tial a m plif ier . th e ad8 138 ca n be us e d as a sin g le- ende d-t o - d if fer e n t ial am plif ier o r as a dif f er en t i al -t o- dif f er en t i al a m p l if ier . th e device is as easy to us e as a n o p am p an d g r ea tl y sim p lif i es dif f er en t i a l sig n a l a m plif ica t ion an d dr i v ing. pseudo diff er ential mod e the ad7934 -6 ca n ha v e tw o ps eudo dif f er en t i a l p a irs b y s e t t ing th e m o d e 0 and m o d e 1 b i ts in t h e co n t r o l r e g i s t er t o 1 a nd 0 , re sp e c t i v e ly . v in + is co nn e c te d to t h e sig n a l s o u r ce, w h ich m u st ha v e an a m p l i t u d e o f v ref (o r 2 v ref d e p e nd i n g on t h e r a nge ch os e n ) t o make us e o f t h e f u l l d y na mic ran g e o f t h e p a r t . a dc in p u t is a p pl ie d t o t h e v in? pin. the v o l t a g e a p plie d t o t h is in p u t pro v i d e s an of f s e t f r om g r ou nd or a p s e u d o g r ou n d f o r t h e v in + in p u t. th e b e n e f i t o f pseud o d i f f e r en t i al in p u t s i s tha t t h ey s e pa ra t e t h e ana l o g i n p u t s i g n a l g r ou nd f r om t h e ad c g r o u nd , a l lo w i n g d c co mmon- m o d e v o l t ages t o b e c a nc e l l e d . t y pic a l l y , t h e v o l t a g e ra n g e f o r t h e v in ? p i n w h il e in pseud o d i f f e r en t i al m o de ca n extend f r o m ?0.3 v t o +0.7 v w h en v dd = 3 v , or f r o m ?0. 3 v t o +1.8 v w h en v dd = 5 v . fi g u re 2 9 s h ow s a c o n n e c t i o n d i ag r a m f o r t h e pse u d o di f f er e n t i al m o de . v in+ v in ? v ref ad7934-6* *additional pins omitted for clarity 04752-037 v ref p-p 0.47 f dc input voltage figure 2 9 . ps eud o differe nt ial m o de conne ction d i ag ram analog input selection a s sho w n i n t a b l e 9, us ers can s e t u p t h e i r a n a l o g in p u t con- f i gura t i o n b y s e t t i n g t h e v a l u es in t h e mo d e 0 a nd mo d e 1 b i t s in t h e con t r o l r e g i s t er . a s s u ming t h e co nf igura t io n has b e en ch os e n , t h er e a r e tw o dif f er en t wa ys o f s e le c t ing t h e analog in p u t t o b e con v er t e d , de p e n d i n g o n t h e st a t e o f t h e s e q0 and se q 1 bit s i n t h e c o n t ro l re g i ste r . traditional m u ltichannel operation (seq0 = se q1 = 0) a n y one of fo ur ana l o g i n p u t chan nels o r t w o p a i r s o f ch an nel s can b e s e l e c t e d fo r con v ersion in an y o r der b y s e t t in g t h e s e q 0 and seq1 b i ts i n t h e c o n t r o l r e g i st er t o 0. the cha n nel t o b e con ver t e d is s e le c t e d b y wr i t ing to t h e address b i t s , add1 and add0, i n t h e con t r o l reg i st er t o p r og ram t h e m u l t i p l e xer p r io r to t h e con v e r sion . th is mo d e o f op era t i o n is t h a t o f a t r a d i t iona l m u l t icha nnel a d c , w h ere e a ch da t a wr i t e s e le c t s t h e nex t ch a n n e l f o r c o n v e r s i o n . fi g u r e 3 0 s h o w s a f l ow ch ar t of t h i s m o d e o f op er a t ion . t h e chan nel conf i g ur a t ions a r e sho w n i n t a b l e 9. power on write to the control register to set up operating mode, analog input, and output configuration. set seq0 = seq1 = 0. select the desired channel to convert on (add1 to add0). issue convst pulse to initiate a conversion on the selected channel. initiate a read cycle to read the data from the selected channel. initiate a write cycle to select the next channel to be converted on by changing the values of bits add2 to add0 in the control register. set seq0 = seq1 = 0. 04752-038 fig u re 3 0 . t r ad it i o nal m u lt i c h a nne l o p erat ion fl ow c h a r t using the se q u en ce r: conse c uti v e se qu en ce ( s eq0 = se q1 = 1) a s e q u e n c e o f co n s e c u t i v e cha n nels ca n b e co n v er te d b e g i n n ing wi th c h ann e l 0, a nd e n din g wi t h a f i nal c h ann e l s e le c t e d b y wr i t in g t o t h e a d d1 a nd add 0 b i ts in t h e co n t r o l r e g i s t er . thi s is do ne b y s e t t i n g t h e s e q0 and s e q1 b i ts i n t h e con t r o l r e g i s t er t o 1. i n this mo de, o n c e th e con t r o l r e g i s t er is wr i t t e n to , t h e n e x t con v ersio n is o n c h a nnel 0, t h e n c h a nnel 1, and s o o n , un t i l t h e ch a nnel s e le c t e d b y t h e a ddr ess b i ts (add1 an d ad d0) is r e ache d .
ad7934-6 rev. a | page 20 of 28 t h e a d c th e n r e t u rn s t o c h a n n e l 0 a n d s t a r t s th e seq u e n ce ag ai n . t h e wr i n put m u s t b e ke pt h i g h to e n s u r e t h a t t h e c o n t r o l r e g i st er is not ac ci de n t al l y o v er w r i t t e n and t h e s e q u e n c e i n ter - r u p t e d . this p a t t e r n con t in u e s u n t i l t h e ad79 34 -6 is wr i t ten to . f i g u r e 3 1 s h ow s t h e f l owc h ar t of t h e c o n s e c ut i v e s e qu e n c e m o d e . power on write to the control register to set up operating mode, analog input, and output configuration. select final channel (add1 and add0) in consecutive sequence. set seq0 = seq1 = 1. continuously convert on a consecutive sequence of channels from channel 0 up to and including the previously selected final channel on add1 and add0 with each convst pulse. 04752-039 figure 3 1 . c o nsec u t iv e sequ enc e mod e fl ow ch art reference section the ad7934 -6 ca n o p era t e wi t h ei t h er t h e o n -c hi p r e f e r e n c e or e x te r n a l re f e re n c e. t h e i n te r n a l re f e re nc e i s s e l e c t e d b y s e tt i n g t h e ref b i t i n t h e in t e r n al co n t r o l r e g i s t er t o 1. a b l o c k dia g ram of t h e i n t e r n a l re f e re nc e c i rc u i t r y i s sho w n i n fi g u re 3 2 . t h e i n te r n a l re f e re n c e c i rc u i t r y i n clu d e s an on - c h i p 2 . 5 v b a n d g a p re f e re n c e a n d a re f e re n c e bu f f e r . wh e n u s i n g t h e i n te r n a l re f e r- en ce , t h e v refin /v refo ut p i n sh ou ld b e de co u p le d to a g n d wi t h a 0.47 f ca p a c i t o r . this in t e r n a l r e f e r e n c e n o t onl y p r o v ides t h e r e fer e n c e fo r t h e a n alog-t o- dig i t a l con v ersi o n , b u t i t ca n als o be us e d ext e r n a l l y in t h e sys t e m . i t is r e co mm e nde d t h a t t h e r e fer e n c e o u t p ut is b u f f er e d usin g a n ext e r n a l pr e c isio n o p a m p b e f o re a p p l y i ng it a n y w he re i n t h e s y ste m . reference ad7934-6 adc buffer 04752 -040 v refin / v refout figure 3 2 . int e rn al r e feren ce c i r c uit b l ock d i ag ra m a l ter n a t ive l y , an exter n al r e fere nce c a n b e a p pli e d t o t h e v ref i n /v ref o ut p i n o f th e ad 79 34 - 6 . an e x t e r n al r e f e r e n c e in p u t i s s e lec t e d b y s e t t in g t h e ref b i t in t h e in t e rnal co n t r o l r e g i st er t o 0. the ex ter n al refer e nce i n p u t r a nge is 0 . 1 v t o v dd . i t i s i m p o r t an t to ensur e t h a t w h en cho o s i ng t h e r e fer e nc e v a l u e, th e m a xi m u m a n a l og i n p u t r a n g e (v in m a x ) i s ne ver g r e a ter t h an v dd + 0. 3 v , i n o r d e r t o c o m p l y w i th th e m a xi m u m ra ti n g s o f th e de vi ce. f o r ex am pl e , if op era t ing i n dif f ere n t i al mo de and t h e re f e re n c e i s s o u r c e d f r o m v dd , th e n th e 0 t o 2 v ref r a n g e ca nno t b e use d . t h is is b e ca use t h e a n alog in p u t si g n a l ra n g e w o uld n o w exte nd t o 2 v dd , w h ich wo u l d exce ed max i m u m r a tin g condi - ti o n s. i n t h e pseud o di f f e r e n t i al m o d e s, t h e us e r m u s t en s u r e tha t (v ref + v in ? ) v dd w h en usin g t h e 0 t o v re f rang e , o r tha t (2 v ref + v in ? ) v dd wh e n u s i n g th e 2 v ref ran g e . i n a l l cas e s, t h e sp e c if ie d r e fer e n c e is 2.5 v . the p e r f o r ma nce o f t h e p a r t wi t h dif f er en t r e fer e n c e v a l u es is s h o w n in f i gur e 9 , f i gur e 10, and f i gur e 11. th e val u e o f t h e r e fer e n c e s e t s t h e a n alog in pu t sp a n a nd t h e comm on- m o d e vo lt age r a nge. e r ror s i n t h e re f e re nc e s o u r c e re s u lt i n g a i n er r o rs in the ad7934-6 tra n sf er f u n c tio n and add t o t h e sp e c if ie d f u l l -s c a le er r o rs o n t h e p a r t . t a b l e 11 lis t s s u i t a b l e v o l t a g e r e fer e n c es a v a i l a ble f r o m analog de vices tha t can b e us ed . f i gure 33 sh o w s a typ i cal co nn ec t i o n dia g ram f o r a n ext e r n al r e f e r e n c e . table 11. e x am ples of suit able voltage re fere nces ref e r e nc e ou t p u t v o ltage initial a c cur a c y (% ma x) op e r a t i n g c u rr en t ( a ) ad780 2.5/3 0.04 1000 a d r 4 2 1 2 . 5 0 . 0 4 5 0 0 a d r 4 2 0 2 . 0 4 8 0 . 0 5 5 0 0 04752-041 1 ad780 nc 8 2 +v in nc 7 3 gnd 6 4 temp 5 o/pselect trim v out v ref 2.5v nc nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f *additional pins omitted for clarity ad7934-6* figure 33. typ i cal v ref conne ction d i agram digital inputs the dig i t a l in p u ts a p p l ie d t o t h e ad7934-6 a r e n o t l i mi t e d b y th e m a xim u m ra ti n g s th a t li mi t th e a n alog i n p u t s . i n s t ead , t h e dig i t a l i n p u ts a pplie d can go to 7 v . t h e y a r e no t r e st r i c t e d b y th e a v dd + 0.3 v limi t tha t is on t h e a n alog in p u ts. a n ot h e r a d v a n t ag e of t h e d i g i t a l i n put s n o t b e i n g re st r i c t e d by th e a v dd + 0. 3 v limi t i s tha t th e po w e r s u p p l y s e q u en cin g i s s u es are avoi d e d. i f a n y of t h e s e i n put s are app l i e d b e f o re a v dd , t h e n t h ere i s no r i sk of l a t c h-up as t h e r e i s on t h e ana l og i n p u ts i f a sig n a l g r ea ter tha n 0. 3 v is a p plied p r io r t o a v dd . v drive input the ad7934 -6 als o has a v dr iv e fe a t u r e. v dr iv e co n t r o ls th e v o l t a g e a t w h ich t h e p a ral l e l i n t e r f ace o p era t e s . v dr iv e allo w s th e a d c to e a s i ly i n te r f a c e to 3 v and 5 v pro c e s s o rs . f o r e x am ple, if the ad7934 -6 is o p era t e d wi th a n a v dd o f 5 v , an d t h e v dr iv e p i n is p o w e r e d f r o m a 3 v s u p p ly , the ad7934 -6 has bet t er d y na mic p e r f o r ma n c e wi t h a n a v dd o f 5 v while s t ill be in g a b le to i n t e r f a c e to 3 v pro c e s s o rs . c a re s h ou l d b e t a ke n to e n su re v dr iv e do es n o t exce e d a v dd b y m o r e than 0.3 v (s ee t h e a b so l u t e m a xim u m r a t i n g s se cti o n ) .
ad7934-6 rev. a | page 21 of 28 parallel interf ace the ad7934 -6 has a f l exi b le , hig h s p e e d , p a ral l e l in t e r f ac e . this in t e r f ace is 12- b i ts wid e an d is c a p a b l e o f o p era t in g i n ei t h er word ( w / b tied hig h ) o r b y te (w/ b ti ed lo w ) m o de . th e co n v s t sig n a l is us e d to ini t ia t e con v ersio n s, a nd w h en o p er a t i n g i n a u to sh u t do wn o r a u to st andb y m o de, i t is us e d to ini t i a t e p o w e r up . a fa l l ing e d ge on t h e co n v s t sig n al is us ed t o ini t ia t e c o n v er- sio n s, a nd i t a l s o p u ts t h e ad c t r ack-and- h o ld in t o t r ack. o n c e th e co n v s t sig n al g o es lo w , t h e b u s y s i g n al g o es hi g h fo r t h e d u r a t i o n o f t h e c o n v ersion. b e t w e e n con vers i on s, co n v s t mu s t be b r o u gh t h i gh f o r a m i n i m u m t i m e o f t 1 . t h is m u s t occu r a f t e r th e 14 th f a l l i ng e d ge of c l k i n ; ot he r w i s e, t h e c o n v e r s i on i s a b o r t e d and t h e t r ack-and- h o ld go es b a ck i n t o t r ack. a t t h e e n d o f t h e co n v ersion, b u s y g o es lo w and can b e us e d t o ac t i va t e an i n t e r r u p t s e r v ice r o ut ine. t h e cs and rd lin e s a r e th en ac tiva t e d in p a ral l e l t o r e ad t h e 12 b i ts o f co n v ersio n da t a . w h en p o w e r s u p p lies a r e f i rs t a p plie d t o t h e de vic e , a r i sin g ed g e o n co n v s t is n e ce ss a r y t o p u t t h e t r ack-and- h o ld in t o trac k. th e acq u isi t io n t i m e o f 125 n s minim u m m u s t be al lo w e d be f o r e co n v s t is b r o u g h t lo w t o in i t ia te a con v ersio n . the a d c th e n g o e s i n t o h o l d o n th e f a ll i n g ed g e o f co n v s t , a nd b a ck i n t o t r ack o n t h e 13 th ri s i n g ed g e o f c l k i n (see f i gur e 34). w h en op er a t ing t h e de vi ce i n a u to sh utdo w n o r a u to st andb y m o de , w h er e t h e ad c p o w e rs do wn a t t h e e n d o f e a ch co n v ersio n , a r i sin g e d g e on t h e co n v s t sig n al is us e d t o po w e r u p th e dev i ce . t 2 t 3 t 20 t 14 t 11 t 9 t 13 t 12 t 10 t convert t aquisition t quiet t 1 12 3 4 5 1 2 1 3 1 4 b a data data old data db0 to db11 db0 to db11 rd cs internal track/hold busy clkin convst three-state three-state 04752 - 004 with cs and rd tied low fi gur e 34 . ad7 934 -6 pa ral l e l inte r f ac eco nver si on and re a d cycl e i n w o r d mo de (w / b = 1)
ad7934-6 rev. a | page 22 of 28 reading data from the a d 7 934-6 w i th th e w / b p i n tie d log i c hig h , t h e ad7934-6 in t e r f ace o p era t es in w o rd m o d e . i n t h is cas e , a sin g l e r e ad o p era t io n f r o m t h e de vice acces s es t h e co n v ersio n da t a -wo r d o n p i n s d b 0 t o d b 11. th e db8/hb e n p i n as s u m e s i t s d b 8 f u n c tion. w i t h th e w/ b p i n tie d t o log i c lo w , t h e ad7934-6 in t e r f ace o p era t es in b y t e m o de . i n t h is cas e , t h e d b 8/hb e n p i n as s u m e s i t s hb en f u n c t i o n . c o n v ersio n da t a f r o m th e ad7 934-6 m u s t be acces s e d in tw o r e ad o p era t io n s wi th 8 b i ts o f da ta p r o v ide d o n d b 0 t o d b 7 f o r e a ch o f t h e r e ad o p era t io n s . the hbe n p i n de ter m i n es w h e t he r t h e r e ad o p era t i o n acces s e s t h e hig h b y te o r t h e lo w b y te o f t h e 12-b i t w o r d . f o r a lo w b y t e r e ad , d b 0 t o d b 7 p r o v ide t h e eig h t ls bs o f the 12-b i t w o rd . f o r a hig h b y te r e ad , d b 0 t o d b 3 p r o v ide t h e 4 m s bs o f th e 12 -b i t w o r d . d b 4 and d b 5 o f the hig h b y te p r o v ide t h e c h a n ne l i d . d b 6 a nd d b 7 a r e al wa ys 0. f i gur e 34 sh o w s th e r e ad c y c l e timin g dia g ra m fo r a 12-b i t t r a n sfer . w h e n o p era t e d i n w o r d m o de , t h e h b en i n p u t do es n o t exist an d o n ly t h e f i rst r e a d o p era t ion is r e quir e d t o acce ss da ta f r o m t h e devi ce . w h en o p e r a t ed i n b y t e m o d e , t h e t w o r e ad c y c l es s h o w n in f i gur e 35 a r e r e q u ir ed t o acces s t h e f u l l d a t a - w ord f r om t h e d e v i c e . the cs and rd sig n a l s a r e ga te d in ter n a l ly a n d l e vel t r ig ger e d a c t i ve l o w . in e i t h e r word mo d e or b y te mo d e , cs a nd rd ca n b e t i e d t o get h er as t h e t i m i n g sp e c if ic a t io n t 10 and t 11 are 0 ns mini m u m. t h is m e an s t h e b u s is co n s t a n t ly dr iv en b y t h e ad7934-6. t h e d a ta i s p l a c e d o n t o th e d a ta b u s a t i m e , t 13 , a f t e r bo t h cs a nd rd g o lo w . the rd ri s i n g ed g e ca n b e used t o l a t c h d a t a out of t h e d e v i c e . a f te r a t i m e , t 14 , t h e d a ta l i n e s b e c o m e th r e e - st a t e d . al ter n a t i v e l y , cs a nd rd ca n b e t i e d p e r m a n en t l y lo w , and t h e co n v ersio n d a t a is va lid and pl a c e d o n to t h e da t a b u s a t i m e , t 9 , bef o r e the fal l ing edg e o f b u s y . no t e t h a t i f rd i s p u l s e d d u ri n g th e c o n v e r s i o n t i m e th e n th i s ca us es a deg r a d a t io n in l i n e a r i t y p e r f o r ma n c e o f a p p r o x ima t e l y 0.25 ls b . readin g d u r i n g con v ersio n b y wa y o f tyin g cs and rd lo w do es n o t ca us e a n y deg r ada t io n. t 11 t 10 t 13 t 15 t 15 t 16 t 16 t 14 t 12 t 17 low byte high byte db0 to db7 hben/db8 rd cs 04752-005 fig u re 3 5 . a d 79 3 4 -6 p a r a lle l i n t e rf a c e r e ad cy c l e ti m i ng f o r by t e m o d e o p erat ion ( w / b = 0)
ad7934-6 rev. a | page 23 of 28 writing data to the a d 7934-6 wi t h w / b t i e d log i c hig h , a si n g l e wr i t e o p er a t ion t r a n sfers t h e f u l l da t a -w o r d on d b 0 t o d b 11 t o th e co n t r o l r e g i s t er o n t h e ad7934-6. th e d b 8/hb e n p i n as s u m e s i t s d b 8 f u n c tion. d a t a wr i t t e n t o t h e ad7934-6 sh o u ld be p r o v ided on th e d b 0 t o d b 11 i n p u t s , w i th d b 0 be i n g t h e l s b o f th e d a t a - w o r d . w i th w/ b tied log i c lo w , t h e ad7934-6 r e q u ir es tw o wr i t e o p era t io ns t o tra n sfer a f u l l 12-b i t w o r d . db8/hb e n as s u m e s i t s h b en f u n c tion. d a ta wr i t t e n t o t h e ad7934-6 sh o u ld be p r o v ided on t h e d b 0 t o d b 7 in p u ts. h b en det e r m i n es w h e t h e r t h e b y te w r it te n i s h i g h b y te or l o w b y te d a t a . t h e l o w b y te of t h e d a t a - w o r d h a s d b 0 b e i n g t h e ls b o f th e full d a ta- w o r d . f o r th e hi gh b y t e w r i t e , h b en s h o u l d b e h i gh , a n d th e d a ta o n th e d b 0 in p u t sh o u ld b e da t a bi t 8 o f t h e 12-b i t w o r d . f i gur e 36 s h o w s th e w r i t e c y c l e ti m i n g d i a g r a m o f th e a d 7 9 3 4 - 6 . w h en op era t e d in w o r d m o de , t h e h b en in p u t do es n o t exis t, a nd o n l y o n e w r i t e o p er a t io n is r e q u ir e d t o wr i t e t h e w o r d o f da ta t o th e device . da ta sh o u ld be p r o v id ed o n d b 0 t o d b 11. w h en op era t e d in b y t e m o de , t h e tw o wr i t e c y cles s h o w n in f i g u r e 3 7 a r e r e q u i r e d t o w r i t e th e full d a ta - w o r d t o th e ad7934-6. i n f i gur e 37, t h e f i rs t wr i t e tra n sf ers th e l o w e r 8 b i ts o f t h e d a t a -w o r d f r o m db0 to db7, a nd t h e s e co nd wr i t e tra n sf e r s th e u p pe r 4 b i ts o f th e da ta- w o r d . w h en wr i t ing to th e ad7934-6 , th e t o p 4 b i ts in t h e hig h b y t e mu s t b e 0 s . the da t a i s l a tche d i n t o t h e de vi c e on t h e r i s i n g e d ge o f wr . the d a ta n e e d s t o be se t u p a ti m e , t 7 , be f o r e t h e wr r i s i ng e d ge and hel d fo r a t i me, t 8 , af ter t h e wr ri s i n g ed g e . t h e cs an d wr sig n al s a r e g a t e d in t e r n al l y . cs and wr can b e tie d t o g e t h er as th e ti m i n g s p eci f i c a t i o n f o r t 4 , and t 5 i s 0 n s mi nim u m (as s umin g cs and rd ha ve no t a l r e ad y b e e n t i e d toget h er) . t 8 t 5 t 7 t 6 t 4 data db0 to db11 wr cs 04752 -002 fig u re 3 6 . a d 79 3 4 -6 p a r a lle l i n t e rf a c e wr it e cy c l e ti m i ng f o r wo rd m o de operat ion ( w / b = 1) t 5 t 4 t 7 t 18 t 18 t 19 t 19 t 8 t 6 t 17 low byte high byte db0 to db7 hben/db8 wr cs 04752-003 fig u re 3 7 . a d 79 3 4 -6 p a r a lle l i n t e rf a c e wr it e cy c l e ti m i ng f o r by t e m o d e o p erat ion ( w / b = 0)
ad7934-6 rev. a | page 24 of 28 power modes of operation the ad7934 -6 has f o ur dif f er e n t p o w e r mo des o f o p era t io n. th e s e m o des a r e desig n e d t o p r o v i d e f l exi b le p o w e r ma na g e - me n t opt i ons . d i f f e r e n t opt i o n s c a n b e cho s e n to opt i m i z e th e po w e r d i s s i p a t i o n / th r o ugh p u t ra t e ra ti o f o r d i f f e r i n g a p plic a t io n s . t h e m o de o f o p era t io n is s e le c t e d b y t h e p o w e r ma na g e m e n t b i ts, pm1 a nd pm 0, in t h e co n t r o l r e g i s t er (s ee t a b l e 8). w h en p o w e r is f i rs t a p p l ied t o t h e ad7934-6, a n o n - ch ip , p o we r - o n re s e t c i rc u i t e n s u re s t h a t t h e d e f a u l t p o we r - up co ndi t i on is n o r m a l m o de. n o t e th a t , a f t e r po w e r - o n , th e tr a c k - a n d - h o l d i s i n h o l d m o d e , a nd t h e f i rst r i si n g e d ge o f co n v s t places t h e t r ack-and - h o ld in t o t r ack m o d e . normal mode (pm1 = pm0 = 0) this m o d e is i n tende d fo r t h e f a stest t h r o ug h p u t r a te p e r f o r m- a n ce b e ca us e t h e us er do es n o t ha v e t o al lo w fo r p o w e r - u p t i mes as s o c i a t ed wi th th e ad7934-6 . i t r e ma in s f u l l y p o w e r e d u p a t a l l tim e s. a t p o w e r - o n r e s e t, this m o de is t h e def a u l t s e t t in g in t h e c o n t ro l re g i ste r . autoshutdown mode (pm1 = 0; pm0 = 1) i n this mo de o f o p era t ion, t h e ad7934-6 a u t o ma tic a l l y en t e rs f u l l sh utd o w n at t h e e n d of e a c h c o n v e r s i on , s h ow n a t p o i n t a in f i gur e 34 and f i gur e 38. i n sh u t do wn m o de , al l in ter n al cir c ui t r y o n t h e de vice is p o w e re d do w n . t h e p a r t r e t a in s info r m a t io n in t h e con t r o l r e g i st er d u r i n g sh u t do wn. t h e t r ack- a nd- h o ld a l s o go es in t o h o ld a t t h is p o i n t, and r e ma in s in h o ld as lo n g as the device is in sh u t do wn. th e ad79 34-6 r e ma in s in sh utd o w n mo d e u n t i l t h e ne x t r i s i ng e d ge of co n v s t (s e e p o in t b in f i gure 34 a nd f i gur e 38). t o k e ep th e de vice in sh ut do w n fo r as lo n g as p o ssi b l e , co n v s t s h o u ld i d l e lo w be tw e e n con v ersio n s as sh o w n in f i gur e 38. o n this r i sin g e d g e , t h e p a r t b e g i n s t o p o w e r - u p and t h e t r ack - an d - h o ld r e t u r n s t o t r ack m o de. t h e p o w e r - u p t i me r e q u ir e d is 10 m s mi ni m u m r e ga r d les s o f w h et her t h e us er is o p era t i n g wi t h t h e in t e r n al o r ext e r n al r e fer e nce . th e us er sh ou ld en s u r e t h a t t h e p o w e r - u p t i m e has e l a p s e d b e fo r e ini t ia t i n g a con v ersio n . autos t an db y mode ( p m1 = 1; pm0 = 0) i n this mo de, t h e ad7934-6 a u to ma tic a l l y en t e rs s t and b y m o de a t t h e e n d of e a ch c o n v e r s i on , s h ow n a s p o i n t a i n f i g u re 3 4 . w h en this m o de is en t e r e d , al l cir c ui tr y o n the ad7934-6 is p o we re d d o w n e x c e pt f o r t h e re f e re nc e a n d re f e re nc e bu f f e r . the t r ack - an d - h o ld a l s o go es i n t o h o ld a t t h is p o in t an d r e ma in s in h o ld as lo n g as the device is in s t an db y . the p a r t r e ma in s in s t andb y un til t h e n e xt r i sin g e d g e o f co n v s t po w e r s u p th e devi c e . th e po w e r - u p tim e r e q u i r ed d e pen d s o n w h et h e r t h e in ter n al o r ext e r n al r e fer e n c e is us e d . w i t h a n e x te r n a l re f e re n c e, t h e p o we r - up t i m e re qu i r e d i s a m i n i m u m o f 600 n s . w h en usin g t h e in t e r n a l r e f e r e n c e , t h e p o w e r - u p t i m e r e q u ir e d is a minim u m o f 7 s. the us er sh o u ld en s u r e t h is p o w e r - u p t i m e has e l a p s e d b e fo r e ini t ia t i n g ano t h e r con v ersion as s h o w n in f i g u r e 38. this r i sin g edg e o f co n v s t also p l a c es t h e t r ack-and- hold b a ck i n t o t r ack m o d e . full shutdow n mode (pm1 = 1; pm0 = 1) w h en this m o de is en t e r e d , al l cir c ui tr y o n the ad7934-6 is p o w e r e d do wn u p o n com p let i on o f t h e wr i t e op er a t ion, t h a t is , on r i s i ng e d ge o f wr . the t r ack- a nd- h o ld e n ters hold m o de a t t h is p o i n t. t h e p a r t r e t a in s t h e info r m a t io n in t h e con t r o l r e g i s t er whil e t h e p a r t is in sh u t do wn. th e ad7 934-6 r e ma in s in f u l l sh u t d o w n m o d e , an d t h e t r ack-and- h o l d i n h o l d m o de, un t i l t h e p o w e r ma na ge m e n t b i t s (pm1 a nd pm 0) in t h e con t r o l r e g i s t er a r e chan g e d . i f a wr i t e t o t h e co n t r o l r e g i s t er o c c u rs w h i l e t h e p a r t is in f u l l s h u t do w n m o de , an d t h e p o w e r ma na g e m e n t b i ts a r e c h a n g e d t o pm0 = pm1 = 0 (n o r mal m o de), t h e p a r t beg i n s t o p o w e r u p o n t h e wr r i sin g e d ge, and t h e t r ack-and- hold r e t u r n s t o t r ack. t o en sur e t h e p a r t is f u l l y p o w e r e d u p b e fo r e a co n v ersion is in i t ia t e d , t h e p o w e r - u p t i me o f 10 m s min i m u m sh o u ld b e a l lo w e d b e fo r e t h e co n v s t fa l l in g e d ge; o t her w is e , in va li d d a t a is r e a d . n o t e t h a t al l p o w e r - u p tim e s q u o t ed a p p l y wi t h a 470 nf ca p a ci t o r o n t h e v refin pi n . t power-up 1 1 14 14 busy clkin convst 04752-048 a b figure 38. autoshu t do wn/autostandb y modes
ad7934-6 rev. a | page 25 of 28 power vs. throughput rate a co n s iderab le ad van t a g e o f p o w e r i n g t h e ad c do wn a f t e r a co n v ersio n is t h a t t h e p a r t s p o w e r co n s um p t ion is sig n if i c a n t l y r e d u ce d a t lo w e r t h r o ug h p u t ra t e s. w h e n usin g t h e dif f er en t p o w e r m o des, t h e ad7934-6 is o n l y p o w e r e d u p f o r th e d u ra t i on o f t h e co n v ersio n . th e r efo r e , t h e a v er ag e p o w e r co n s um p t io n p e r c y cle is sig n if ica n t l y r e d u ce d . f i gur e 39 sh o w s a p l o t o f th e po w e r v s . th e th r o ugh p u t ra t e w h e n o p e r a t i n g i n a u to st andb y m o de fo r b o t h v dd = 5 v a nd 3 v . f o r exa m p l e , if th e de vice r u n s a t a t h r o ug h p u t ra t e o f 10 ks ps, th en t h e o v eral l c y c l e tim e w o u l d b e 100 s. i f t h e maxim u m c l k i n f r eq ue n c y o f 10 mh z i s used , t h e co n v er s i o n tim e acco un ts f o r o n l y 1.315 s o f th e o v eral l c y c l e tim e while t h e ad7938-6 sta y s in s t an db y m o de f o r th e r e main der o f th e c y c l e . i f a n ext e r n al r e fer e n c e is us e d , t h e p o w e r - u p t i m e r e d u ces t o 600 n s ; t h er ef o r e , t h e ad7934-6 r e ma in s in s t andb y f o r a g r e a t e r t i m e in e v er y c y c l e . a d di t i o n al l y , t h e c u r r en t co n s um p t io n w h en con v er tin g s h o u l d be lo w e r tha n t h e s p ecif ie d maxim u m o f 1.5 ma o r 1.2 ma wi t h v dd = 5 v o r 3 v , re sp e c t i v e ly . f i gur e 40 sh o w s a p l o t o f th e po w e r v s . th e th r o ugh p u t ra t e w h en op era t i n g in n o r m al m o de fo r b o t h v dd = 5 v a nd 3 v . a g a i n, w h en usi n g a n ext e r n al refer e n c e , t h e c u r r en t co n s um p t io n w h e n con v er t i n g is lo w e r t h a n t h e sp e c if ie d max i m u m. i n b o t h plo t s, t h e f i gur e s a p ply w h e n usin g t h e i n te r n a l re f e re n c e. throughput (ksps) power ( m w) 2.0 0.2 0.4 0.6 0.8 1.2 1.6 1.0 1.4 1.8 0 0 2 0 4 0 6 0 8 0 120 100 04752-029 t a = 25 c v dd = 5v v dd = 3v figure 39. power vs. thr o ughput in au tostandby mod e u s ing intern al r e fe renc e throughput (ksps) power ( m w) 7 4 5 6 0 3 2 1 0 100 200 300 400 500 700 600 04752-030 t a = 25 c v dd = 5v v dd = 3v figure 4 0 . po wer v s . thr o ughput in n o rm al mode u s ing i n tern al r e f e re nce microprocessor interfacing ad7934-6 to adsp-21xx interface f i gur e 41 sh o w s th e ad7934-6 in t e r f ace d t o t h e ads p -21xx s e r i es o f ds p s as a m e m o r y -ma p p e d de vic e . a sin g le wai t st a t e co u l d b e neces s a r y t o in t e r f ace th e ad7934-6 to th e ads p - 21xx, dep e n d ing o n t h e clo c k sp e e d o f t h e d s p . the wai t st a t e c a n b e p r o g r a m m ed v i a th e d a ta m e m o r y w a i t s t a t e c o n t r o l r e g i s t er o f t h e a d s p -21xx (s e e t h e ads p -21xx fa mil y u s er s m a n u al fo r details). th e fol l o w in g in str u c t io n r e ads f r o m the ad7934-6: mr = dm ( ad c ) w h er e: ad c is t h e addres s o f th e ad79 34-6. ad7934-6 1 adsp-21xx 1 wr rd db0 to db11 d0 to d23 a0 to a15 dms ir q2 busy cs convst dsp/user system wr rd 1 additional pins omitted for clarity. address bus data bus address decoder 04752-044 figure 4 1 . int e rfa c i n g to the a d sp- 21x x
ad7934-6 rev. a | page 26 of 28 ad7934-6 to adsp-21065l interface f i gur e 42 sh o w s a typ i cal in t e r f ace between t h e ad7934-6 and th e ads p -2106 5l s h ar c p r o c es s o r . this in ter f ace is a n exa m ple o f o n e o f t h r e e d m a ha n d s h ak e mo de s. th e msx co n t r o l line is ac t u al l y thr e e m e m o r y s e le c t l i n e s. i n t e r n al ad d r 25C24 a r e d e co de d in to ms 3-0 . th es e li n e s a r e t h en as s e r t e d as chi p s e le c t s. the dm a r 1 (d ma r e q u es t 1) is us ed in this s e t u p as t h e i n t e r r u p t t o sig n al t h e e nd o f t h e con v ersio n . th e r e s t o f th e i n t e rfa c e i s a sta n d a r d h a n d s hakin g o p era t i o n . ad7934-6 1 adsp-21065l 1 wr db0 to db11 d0 to d31 addr 0 to addr 23 ms x dm ar 1 busy cs convst dsp/user system wr rd rd 1 additional pins removed for clarity. address bus address bus data bus address latch address decoder 04752-045 fi gur e 42 . int e r f ac ing to the adsp -2 10 65 l ad7934-6 to tms32020, tms320c25, and tms320c5x inter f ace p a ral l e l in t e r f ac es betw een t h e ad7934-6 and t h e t m s32020, t m s320c25, and t m s320c5x fa mil y o f ds p s a r e s h o w n in f i gur e 43. th e m e m o r y -ma p p e d addr es s ch os en fo r t h e ad7934-6 s h o u ld b e c h os en t o fal l in the i/o m e m o r y s p ace o f th e ds p s . th e p a ral l e l in t e r f ace o n t h e ad7934 -6 is fas t en o u g h t o in ter f ace t o t h e t m s32020 wi th n o extra wa i t s t a t es. i f hig h s p e e d g l ue log i c de vices, s u ch as t h e 74as, a r e u s e d t o dr i v e t h e rd a nd t h e wr lin e s w h en in t e r f ac in g t o th e t m s320 c25, n o wai t st a t e s are ne c e ss ar y . h o we ve r , if sl o w e r l o g i c is u s e d , da t a ac c e ss e s c o u l d b e sl o w e d su f f i c i e n t l y w h e n re ad ing f r om, and wr i t in g to , t h e p a r t t o r e q u ir e t h e in s e r t ion o f o n e wa i t st a t e . e x tra wa i t sta t es a r e n e cess a r y when usin g the t m s320c5x a t th eir fas t es t c l o c k s p eeds (s ee t h e t m s320c5x u s er s g u ide f o r det a i l s). d a t a is r e ad f r o m t h e a d c usi n g t h e fol l o w ing in st r u c t io n: in d , ad c w h er e: d is t h e da t a mem o r y addr ess. ad c is t h e ad7934-6 addr ess. ad7934-6 1 tms32020/ tms320c25/ tms320c50 1 wr rd db11 to db0 dmd0 to dmd15 a0 to a15 is ready in t x busy cs en convst dsp/user system tms320c25 only r/w strb 1 additional pins omitted for clarity. address bus data bus address decoder 04752-046 msc fi gur e 43 . int e r f ac ing to the tms320 20 / c 2 5 / c 5 x ad7934-6 to 80c186 interface f i gur e 44 sh o w s th e ad7934-6 in t e r f ace d t o t h e 80c186 micr o p ro c e ss o r . the 8 0 c186 d m a con t r o l l er p r o v ides tw o i n de p e nde n t hi g h sp e e d d m a cha n nels w h ere da t a t r an sfer can o c c u r b e t w e e n me m o r y and i/o s p aces . e a ch da t a t r a n sfer co n s um e s t w o b u s c y c l es , o n e c y c l e t o fet c h da t a a n d t h e o t h e r t o s t o r e d a ta . a f t e r th e a d 79 3 4 - 6 h a s f i n i s h ed a c o n v e r si o n , th e b u s y l i ne ge ner a tes a d m a re quest to c h an nel 1 (drq1) . b e c a us e o f t h e i n t e r r upt, t h e p r o c e s s o r p e r f o r ms a d m a re a d o p e r a t io n t h a t also r e s e ts t h e in t e rr u p t la t c h. s u f f ici e n t p r i o r i t y m u s t be as s i g n ed t o th e d m a c h a n n e l t o en s u r e tha t th e d m a r e q u e s t i s se r v i c e d b e f o r e th e c o m p le ti o n o f th e n e x t c o n v e r s i o n . ad7934-6 1 80c186 1 wr db0 to db11 ad0 to ad15 a16 to a19 ale drq 1 busy cs qr s convst p/user system wr rd rd 1 additional pins omitted for clarity. address/data bus address bus data bus address latch address decoder 04752- 047 figure 4 4 . int e rfa c i n g to the 8 0 c1 86
ad7934-6 rev. a | page 27 of 28 application hints grounding and layout the printed circuit board that houses the ad7934-6 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. generally, a minimum etch technique is best for ground planes since it gives the best shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the ad7934-6 as possible. avoid running digital lines under the device as this couples noise onto the die. the analog ground plane should be allowed to run under the ad7934-6 to avoid noise coupling. the power supply lines to the ad7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. evaluating the ad7934-6 performance the recommended layout for the ad7934-6 is outlined in the evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7934-6 evaluation board, as well as with many other adi evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7934-6. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7934-6. the software and documentation are on the cd that ships with the evaluation board.
ad7934-6 rev. a | page 28 of 28 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 fig u re 4 5 . 28-l e ad thin shr i nk s m a l l outlin e p a ck age [t ssop] (r u - 28) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model t e mper a t ur e r a nge linearit y err o r (lsb) 1 p a ck age descri ptions p a ck age o p tion ad7934bru-6 ?40c to +85c 1 28-l e ad tssop ru-28 ad7934bru-6r eel7 ?40c t o +85c 1 28-l e ad tssop ru-28 ad7934bruz - 6 2 ?40c to +85c 1 28-l e ad tssop ru-28 ad7934bruz - 6 r eel7 2 ?40c to +85c 1 28-l e ad tssop ru-28 e v al - a d7934-6 c b 3 e v alua t i o n boar d e v al - c ont r ol brd2 4 c o n t r o ll e r bo ar d 1 linearity error here re fer s to integral li nearity error. 2 z = pb-free part. 3 this can be us ed a s a s t and a l o ne e v aluatio n bo ard o r in conjunct i o n with the e v al uatio n bo ard co ntro l le r f o r e v al ua tio n /d e m o n s tration purpose s . 4 th e eva l ua t i on boa r d con t r ol ler i s a co m p let e un i t t h a t a l l o ws a p c t o con t r ol a n d com m u n i ca t e wi t h a ll an a l og d e v i ces eva l ua t i o n boa r ds en di n g i n t h e c b designators. the fo llowing needs to b e or dered to obtain a complete evaluation kit: the adc eval uation board (e.g . eval-ad7934c b), the eva l -c ontrol brd2, and a 12 v ac trans f o r me r. s e e the re le vant eval uatio n bo ard te chnical no te f o r mo re de tail s . ? 2005 analo g de v i ces, inc. all rights reserve d . tr adem ar ks and registered tra d emar ks are the prop erty of their respective o w ners . d04752-0-10/05(a)

▲Up To Search▲

Price & Availability of AD7934BRUZ-6

	To Download AD7934BRUZ-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .